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EPC120 fully integrated light-barrier chips with 2-wire bus interface general description the EPC120 is a general purpose, fully integrated self-contained cmos circuit to be used in light-barrier applications. the chips contain a controller which drives an led, typically an ir-led. the led is used in a pulsed mode to increase the signal-to-noise ratio even when there is very strong sunlight biasing the photo diode. it contains also a high sensitive photo diode amplifier and a signal conditioning circuitry to cancel unwanted environmental light including strong sunlight and pulsed light sources. the receiver is built around a synchronous demodulator circuitry. two output signals with a different threshold level are implemented in order to trigger the light barriers output or to indicate light reserve. the chips also include a power supply circuitry to establish all internally required voltages from the 2-wire bus. they contain a 2-wire communication interface which is capable to operate as many as 1023 devices on a 2-wire bus at a speed of up to 2mbit/s over the power supply. this feature allows to design of a distributed light barrier system. features ? fully integrated light barrier chip ? needs just a photo diode and an led with an led driver ? configurable ? high speed 2-wire bus ? integrated clock generator ? csp10 package with very small footprint or standard qfn16 package available ? versions without 2-wire bus interface available (epc11x family) applications ? light barriers ranging from millimeters to tens of meters ? smoke detectors ? liquid detectors functional block diagram functional block diagram epc70x lst v o l t a g e r e g u l a t o r parameter memory 2-wire com interface 2-wire com interface so si en cs vdd33 pd 19.10.2010 page 1 ... file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . led d1 v led f vdd18 signal processor processor spi controller gnd vdd led sck ? 2011 espros photonics corporation characteristics subject to change without notice 1 datasheet epc12x - v2.1 www.espros.ch
EPC120 absolute maximum ratings (notes 1, 2) recommended operating conditions voltage to any pin except v dd supply voltage on 2-wire bus v dd programming voltage on 2-wire bus v dd input current at any pin except led power consumption with maximum load storage temperature range (t s ) lead temperature solder, 4 sec. (t l ) -0.3v to vdd+0.3 v -0.3v to + 8.0v -0.3v to +8.0v -6ma to +6 ma 125mw -55c to +155c +260c operating voltage on 2-wire bus v dd programming voltage on v dd operating temperature (t o ) relative humidity (non-condensing) min. 4.5 7.0 -40 +5 max. 5.5 8.0 +85 +95 units v v c % note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. recommended operating conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. for guaranteed specific - ations and test conditions, see electrical characteristics. note 2: this device is a highly sensitive cmos ac current amplifier with an esd rating of jedec hbm class 0 (<250v). handling and assembly of this device should only be done at esd protected workstations. electrical characteristics v dd = 4.5v 5.5v, -40c < t a < +85c, unless otherwise specified general data symbol parameter conditions/comments values units min. typ. max. v pp ripple on supply voltage, peak to peak 2-wire interface v det input pulse i pd nst 50mv 48na 150 mv 100mv 72na 350 mv 200mv 108na 600 mv i dd_op current consumption in operation mode i pd = 0 ma 2 ma v det detection level for 2-wire interface configurable 50 200 mv i mod modulation current for 2-wire inter - face 6.4 9.8 ma f clk reference clock internal oscillator 1 mhz d f clk temperature drift of the oscillator 640 ppm/k v pup power-up threshold voltage the voltage at vdd33 when the device starts up 2.4 3 v v ih input logical high (v n can be either vdd or vdd33) 0.7 *v n v n v v il input logical low (v n can be either vdd or vdd33) gnd 0.3 *v n v i leakd input leakage current 10 a v oh output high voltage @ 4ma sink except pin sck/led v dd - 0.5 v v ol output low voltage @ 4ma source 0.5 v i sck/led source current @ pin sck / led 0.7 1.3 ma v hist schmitt trigger hysteresis 0.1 v r pu pull-up resistor 30 200 k i pddc dc photo diode current generated by ambient light with no effect to the sensitivity 0.0 2 ma c pd photodiode capacitance photodiode capacitance 40 pf i n_imin input related noise @ i pddc =0 15 na rms i n_imax input related noise @ i pddc =i pddcmax 20 na rms i pdn photo current sensitivity, normal threshold parameter sensn = 011 (60na). t pulse = 6 s photodiode pulse to generate a status pulse detected 45 60 75 na i pdh photo current sensitivity, upper threshold parameter sensh = 011 (96na). t pulse = 6 s photodiode pulse to generate a status pulse detected 1.4 1.6 1.8 i pdn ? 2011 espros photonics corporation characteristics subject to change without notice 2 datasheet epc12x - v2.1 www.espros.ch
EPC120 symbol parameter conditions/comments values units i pulse maximum input pulse current if the input current pulse is above this level, the recovery time t rec is undefined (refer to section 'other parameters') dependent on settings a t pulse led pulse length programmable between 1 and 8 s t relax relaxation time after a strong current pulse (i pulse = 100a) dependent on settings s other parameters (typical values, t amb = 25c, v dd = 5.0v) ? 2011 espros photonics corporation characteristics subject to change without notice 3 datasheet epc12x - v2.1 www.espros.ch figure 1 : input sensitivity vs. led pulse width 0 1 2 3 4 5 6 40 50 60 70 80 90 100 110 120 pulse width [us] s e n s i t i v i t y [ n a ]
EPC120 connection diagrams top view cs outn/ so pd gnd vdd en/ si led/s ck vdd33 nc vdd18 3 2 1 10 5 4 7 6 8 9 top view 05.12.2011 page 1 ... file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 s o c s pd gnd v d d v d d 1 8 v d d 3 3 led/ sck en/ si 10-pin chip scale package (csp) 16-pin qfn package 10-pin csp 16-pin qfn pin name type description 1 9 vdd power supply positive power supply 2 7 gnd power supply negative power supply pin. 3 6 pd analog input photo diode input. 4 4 cs digital input spi interface: chip select. active low, with pull up 6 1 so digital output spi interface serial out 7 15 si digital output spi interface serial input 8 14 led sck digital in / out light barrier: led control spi interface: shift clock 9 12 vdd33 power supply decoupling a power supply filter capacitor is connected to this pin. 10 10 vdd18 analog out 1.8v regulator output, used to connect a filter capacitor. must not be used to supply any other circuits. 5 2 nc not connected. leave that pin floating. n/a 3, 5, 8, 11, 13, 16 nc not connected. connect this pin with vss. ? 2011 espros photonics corporation characteristics subject to change without notice 4 datasheet epc12x - v2.1 www.espros.ch
EPC120 1. application information the EPC120 chip set is a general purpose cmos integrated circuit for light barrier applications. up to 1023 devices may be connected to two respectively fo ur wires in parallel. each device can be individually addressed by an epc100 chip which acts as the interface between a microcontroller and the 2-wire bus. it manages the bus traffic between the microcontroller and the individual EPC120 elements. programmable fuses i.e. for the address, sensitivity, led light pulse width, etc. allow the device to be parametrized in the final system (otp memory). the bus controller activates the emitting side of the EPC120 and reads the status of the levels at the photodiode input. the status of the answers to the interface chip can be 'no light pulse received', 'low level light pulse received' and 'high level light pulse received'. each chip can be put into 'standby mode' or 'operating mode' to reduce power consumption. during 'standby mode', power consumption is reduced and the photo diode is shorted. in the 'operation mode', the device is active and ready to receive a light pulse generated by an led activated by the led pin. during a scan, the bus controller addresse s one device after the other and fetches the light barrier status. this manual describes the various operation and programming modes in order to use EPC120. for the interface chip epc100 please refer to the epc10x reference manual. 2. hardware design information figure 2 shows the EPC120 as an example in a long range light barrier application as a single bus module in a bus-chain configuration with minimal part count. the led emits a light pulse when the chip is addressed by the bus controller. light of the led is reflected from a reflecting object or a retro reflector back to the photo diode pd. if the received light is strong enough it triggers the internal thresholds outn/h. the status of the receiver result can be read by the bus controller. cs led/sck si so pd vdd33 vdd EPC120 gnd vdd18 pd c3 r3 2r2 ir led, i.e. tsml1000 r1 100r c1 100f low esr r2 10k c4 gnd 2-wire bus (data & power) vdd track for leds i.e. epc300 100nf t1 bc846 t2 bc807-40 4.7nf gnd track for leds vdd for 2-wire bus (data & power) b u s c o n t r o l l e r 1 st bus module n th bus module figure 2 : long range light barrier chain application with minimal part count the output to drive the led is a current source capable to drive typically 1ma. for a high performance light barrier, an led peak current of up to 2a is needed. to generate such a high led current, an external amplifier is necessary. the circuitry in figure 2 is a simple implementation of such an amplifier. the complementary darlington circuit with t1 and t2 and r2 and r3 does the job. in order to avoid interference on the supply voltage, the supply is isolated (filtered) with r1 and c1. the high peak led pulse current is delivered by the capacitor c1, which itself is charged more or less constantly by r1. make sure, that there is no coupling of the high led current to the ground and the supplies of the EPC120 or to the cathode of the photo diode. this driver amplifier operates with a vdd led in a range of 5 to 30 vdc. design precautions the sensitivity at pin pd is very high in order to achieve a long operation range of light barriers even without lenses in front of the ir led and/or the photo diode. thus, the pin pd is very sensitive to emi. special care should be taken to keep the pcb track at pin pd as short as possible (a few mm only!). this track should be kept away from the ir led signal tracks and from other sources which may induce unwanted signals. it is strongly recommended to cover the chip, the photodiode and all passive components around the chip with a metal shield. a recommended part is shown in figure 3 . t he pins at the bottom are to solder the shield to the pcb with electrical connection to gnd. the hole in the front is the opening window for the photo diode. the back side of the pcb below the sensitive area (pd, EPC120) shall be a polygon connected to gnd to shield the circuit from the back side as well. ambient light photodiode dc current can be generated by ambient light, e.g. sun light. dc currents at pin pd do not generate a dc output signal. however, if i pddc is above the stated maximal value, the input is saturated which blocks the detection of ac current pulses. ? 2011 espros photonics corporation characteristics subject to change without notice 5 datasheet epc12x - v2.1 www.espros.ch figure 3 : recommended emc shield
EPC120 3. system concept in a system with several reflective light barrier beams, each individual light barrier contains an emitter and a receiver. they are located at the same place. as a receiver acts a photodiode and as an emitter a led. both can be controlled by only one single EPC120. in contrast to the epc11x-family, which are also light barrier chips, the EPC120 can be used in a large distributed system. the devices are synchronized over the 2-wire bus line, organized by one epc100 and a microcontroller. figure 4 shows a typical distributed light barrier setup with five elements. each element consist of an EPC120, an emitter (led), a recei ver (photodiode) and a few other components. every element is connected to the 2-wire bus 1 , which is controlled by a microcontroller through an epc100. because every EPC120 element has a unique address, the microcontroller has individual access to all bus components. each of the EPC120 elements sends light, typically infrared light, focused towards a reflector or an object. it reflects the light back to the photodiode. if multiple sensors like this would be operated in close proximity, scattered light from all sensors are probably reflected to the receivers. this would lead to false triggering. thus, a sequential operation mode has to be implemented. basically, a master controller activates one sensor after the other and reads back the status of each individual light beam. 1 if the led pulse current is rather high, i.e. 1 a, two separate bus wires for the led supply current are needed. please refer to error: reference source not found for detailed information. ? 2011 espros photonics corporation characteristics subject to change without notice 6 datasheet epc12x - v2.1 www.espros.ch figure 4 : system overview micro controller out 2-wire bus EPC120 with pd and led bus interface (epc100) bus termination 50, 100nf spi- interface light cone generate d by the led active lig ht beam ? ? ? ? ?
EPC120 in more detail, such a sequential operation is typically like as follows: 1. the first EPC120 element is turned on (active mode). 2. on a second command this element sends a short light pulse towards his reflector or object, forming the active light beam ? . 3. if there is no obstacle between EPC120 and his reflector, the element receives this light pulse and stores it into a local memory. 4. the bus controller reads out the content of the memory in the EPC120 chip and stores the status (light beam interrupted or not interrupted) into its data memory. 5. finally, EPC120 is turned off (standby mode). this sequence, which is also called 'scan', is repeated until all beams are checked and their status is stored in the beam status memory of the bus controller . the above mentioned sequence is repeated until power is switched off. because of the fact, that an object can enter into a light beam right after a beam has been checked with the above mentioned procedure, up to two full scan sequences are necessary to reliably detect an object. thus, the overall maximum response time of the system will be t r = 2 ? n ? t beam t eval (1) where t r = response time of the system n = number of elements or light beams t beam = time to evaluate one beam t eval = time to evaluate the beam status memory and generate the output signal for further reference in optical design considerations please refer to the respective application notes available from epc. figure 5 shows the EPC120 in a distributed light barrier system application. the epc100 acts as a bus controller. c gnd vdd c vdd r led + i led - i led element 1 r led element 2 vdd pd vdd33 EPC120 gnd led r led element n b u s t e r m i n a t i o n 5 0 1 0 0 n f vdd pd EPC120 gnd led vdd33 vdd vdd33 epc100 gnd so sck si cs vdd pd vdd33 EPC120 gnd led figure 5 : EPC120 in the light barrier application as receivers and the interface chip to the microcontroller from the point of view of the microcontroller , the whole system looks like a single device with several addressable sensors: the microcontroller activates one EPC120 element and fetches the results after a predefined time. in the circuit in figure 5 , the led current is defined by a common current source in the i led line. the resistor r led limits the current through the led and is not needed in non-safety applications. if such a resistor is inserted, a failure mode can be detected, if more than one led is active due to a short circuit or a failure in the epc100. it is also possible to have a common voltage supply and to generate the led current by a resistor. ? 2011 espros photonics corporation characteristics subject to change without notice 7 datasheet epc12x - v2.1 www.espros.ch
EPC120 4. 2-wire bus the 2-wire bus and the power supply utilize the same two wires. the data is transmitted by modulating the current on the power-line. the modulated current, together with the resistor in the power supply, produce a voltage signal on the line. all devices receive this signal. the system is designed to operate with a line impedance of 50 (5%). an inductor in parallel of the resistor or a dc regulator with a lowpass feedback shape the pulses and keep the the dc voltage drop over the resistor low. the required corner fre quency of this l/r-filter is listed in the table below. the communication interface has been designed to be used for line lengths of up to 100m and with up to 1023 sensor devices. for line lengths of up to 3m it is possible to operate the line without termination 2 . above this length the line has to be terminated by a resistor of 50 (5%) which is equal to the line impedance and a capacitor of 100nf in series. the data rate on the 2-wire bus is set by the parameter drate. it also defines t scanmin (refer to chapter error: reference source not found on page error: reference source not found ) and the required inductor according to table 1 . the maximum data rate allowed on the 2-wire bis is depending on the bus length. the longer the bus wire, the lower the data rate. table 1 shows the possible bus wire length according to the data rate. drate k data rate on the 2-wire bus minimal data rate required on spi interface corner frequency l/r inductor bus wire length 3 00 8 250 kbit/s 300 kbit/s 0.5 mhz 16h 12 100m 01 4 500 kbit/s 600 kbit/s 1 mhz 8h 6 12m 10 2 1 mbit/s 1.2 mbit/s 2 mhz 4h 3 6m 11 1 2 mbit/s 2.4 mbit/s 4 mhz 2h 3m table 1 : data rate of the 2-wire communication the default value of drate is 00. the parameter drate has to be identical for all devices on one physical 2-wire bus. the spi bus should be faster than the 2-wire bus, otherwise the communication does not work. since the command length dependent on the command type, the delay time to the next command has to be adjusted to the previous command. the time delay can be calculated with the given data length in table 7 on page 19 . the parameter cdet defines the optimal signal amplitude for the receiver. the maximum rate at pin vddr (5.5v) should not be exceeded and signals which are smaller than 70% of the recommended values are not detected. since the command length is dependent on the command type, the delay time to the next command has to be adjusted to the previous command. the time delay can be calculated with the given data length in table 7 on page 19 . the data handling chain of the 2-wire communication channel is shown in figure 6 . 2 dependent on the electro-mechanical design and the bus location of the edge, the termination network can be necessary. it is in the responsibility of the system designer that the data integrity on the bus is guaranteed. data integrity can be tested by readout bus transmission errors. it is strongly recommended to do that during type qualification during emi qualification tests . 3 the effective length is dependent on the electro-mechanical design of the edge. the values in the table are indicative only. ? 2011 espros photonics corporation characteristics subject to change without notice 8 datasheet epc12x - v2.1 www.espros.ch command data original message parity bits added manchester encoder current sink line filter a/d converter manchester decoder + error detection error correction received message command data receiver transmitter figure 6 : data handling
EPC120 figure 7 shows the different messages with the parity bits. from the interface to the sensor/transmitter device the normal command is used except for the register write command. in the other direction only the register readout has a different format. notice the different start bits which identify the direction of the transmission: 00 for the direction interface to sensor devices and 01 in the other direction. between the telegrams, an idle time of 2 clock periods are need to detect the start of the transmission. figure 7 : message structure bus wire considerations the electromechanical design of a system using multiple epc10x devices on a twisted pair cable with an impedance of typically 100 ohms has an impact on the overall impedance of the system. figure 8 shows the change of the cable impedance with smaller element pitch. figure 8 : line impedance as a function of the element pitch on a 100 ohm twisted pair cable it is highly recommended to terminate the bus line on both sides with an ac terminator network (shown in figure 9 ) which matches the overall impedance of the system according to figure 8 . in order to avoid high dc currents in the termination resistor, a capacitor of 100nf should be connected in series to the termination resistor. ? 2011 espros photonics corporation characteristics subject to change without notice 9 datasheet epc12x - v2.1 www.espros.ch figure 9 : bus termination network r t 100nf a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 c 0 c 1 c 2 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 device address command parity bits a 0 a 1 a 2 a 8 a 9 c 0 c 1 c 2 p 0 p 1 p 8 p 9 r 0 r 1 r 2 r 3 r 4 d 0 d 1 d 14 d 15 p 0 p 1 p 8 p 9 device address command parity bits parity bits data register p 0 p 1 p 8 p 9 parity bits d 0 d 1 d 9 d 10 data a 0 a 1 a 2 a 8 a 9 device address r 0 r 1 r 2 r 3 r 4 d 0 d 1 d 14 d 15 p 0 p 1 p 8 p 9 parity bits data register normal command write command results register readout 1.0 1.8 3.2 5.6 10.0 17.8 31.6 56.2 100.0 0 20 40 60 80 100 120 pitch [cm] i m p e d a n c e [ o h m ]
EPC120 another aspect is the distribution velocity of the electrical signals on the 2-wire bus. since the bus wire itself as well as the individual elements on the bus present a significant capacitance, the distribution velocity decreases with the number of elements and the pitch between the elements. it is important that the overall delay is less than 50% of the clock period of the transmission. e.g. if the system is operated with 2 mbit/s data rate, the max. accepted delay must not be more than 125ns. figure 10 shows, that a system operated at the full speed of 2 mbit/s, a cable length of up to 5m are possible with an element pitch down to 1cm. example: if we have a system that contains 100 elements in a pitch of 10cm, the total bus length is 10m. according to figure 10 , the delay time of a proper terminated bus is a little bit more than 100ns. thus, such a system can be operated with the full speed of 2mbit/s. bus signal waveform figure 11 pictures the manchester encoding and the signal on the bus. the signal on the bus can be monitored with an oscilloscope and should look like in the drawing. cdet is the threshold set in the 2-wire communication receiver of the chip to detect the communication signal on the bus. this parameter, described in table 6 and table 10 , can be adjusted to mach the specific system requirements. thus, the voltage swing v s of the communication signal on the bus shall match this setting. a good principle is that the voltage swing v s measured on the bus should be min. 25% and max. 150% above the cdet value. example: if cdet is set to 200mv, the voltage swing v s should be in a range of 250 to 500 mv. ideal for this setting is a swing voltage v s of 400mv. attention: make sure that the voltage swing v s is in the given tolerance range at every physical location of the bus. due to reflections in the cable, losses of the wires (capacitive, inductive, and resistive), and the high bandwidth of the communication signals, significant differences can occur. ? 2011 espros photonics corporation characteristics subject to change without notice 10 datasheet epc12x - v2.1 www.espros.ch message manchester signal on bus t datarate c d e t v s figure 11 : manchester encoded signal on the bus figure 10 : delay vs pitch. parameter: line length [m] 1 1.78 3.16 5.62 10 17.78 31.62 56.23 100 10 18 32 56 100 178 316 562 1000 1 2 3 5 10 20 50 100 pitch [cm] d e l a y [ n s ]
EPC120 parameter memory the EPC120 device contains a memory to store the application parameters. the following classes of data are stored on each device: ? unique chip id and chip adjustments (factory set) ? physical device address in the application, representing the beam number ? application parameters this data can be permanently stored in a read-only memory 4 and is mirrored in a volatile memory 5 . at power up, the data (except the chip id) is copied from the rom to the ram. during operation, the data from the ram is used. both memories are organized in 16 registers at 16 bits each. the data can be accessed on a 16-bit register base. the following table shows the memory organization: non-volatile memory address range (register no.) volatile memory address range (register no.) description 0 - 3 16 C 19 application parameters 4 - 6 20 C 22 trim values, factory set 7 23 device address 8 C 15 - chip id, factory set - 24 C 31 for factory test purpose. read only. table 2 : memory map overview as shown in the table above, registers 0 C 3 and 7 are used for configuring the chip in the application. before the devices can be used in a given light curtain system, the required application parameters and the physical address of the chip in the system have to be stored into the devices memories. the following table shows a parameter memory overview: parameters in white fields only shall be programmed. never change the memory content of gray marked cells. because only complete registers can be programmed, the bits which are gray marked must be set to zero. the ram can only be written, if the corresponding rom memory hasnt been written before or if the volatile mode is active (vmode, refer to table 3 on page 11 ). the last bit of each 16-bit rom register serves as write inhibit bit. to write to the rom, the microcontroller has to write to the ram first. from there, the microcontroller can first double check the data integrity. when a memory section is verified, the content can be transferred from the ram memory using the command prog to the rom (refer to chapter command prog ). the device is fully operational as well without programming the rom but data will be lost at power down. operating the chips in this mode is helpful during the development of the product. however, in the final application, the parameters must be stored into the rom memory. 4 the non-volatile memory is a one-time-programmable memory (otp). once the memory is programmed, the programmed values cannot be overwritten anymore! this memory type is hereinafter called rom. 5 hereinafter called ram. ? 2011 espros photonics corporation characteristics subject to change without notice 11 datasheet epc12x - v2.1 www.espros.ch figure 12 : detailed memory map rom ram 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 16 vmode mode soff drate tstmp tpulse pol fusebit 1 17 tper fusebit 2 18 tset sens ivcoff slow sensh sensn / vthrled fusebit 3 19 cdet c2x 4 20 trimming 5 21 6 22 7 23 address device address 8 24 chip id chip id 9 25 10 26 11 27 12 28 13 29 14 30 15 31 application parameters
EPC120 5. parameter setting registers 0/16 parameter name register no. bit no. function ram rom fusebit 0 16 0 this bit will automatically be set when register 16 is programmed. 0 values 0 register 16 is not programmed 1 register 16 is programmed pol 0 16 1 polarity of the led pulse. setting is depending on the led driver circuitry. 1 values default setting 0 active low x 1 active high tpulse 0 16 4..2 pulse length of the light pulse. setting is dependent on the led type, the led current, the required response time of the system, the scan rate, the operating range, the lens, etc. 4 3 2 values default setting recommended setting 0 0 0 1s x 0 0 1 2s 0 1 0 3s 0 1 1 4s 1 0 0 5s x (typical setting) 1 0 1 6s 1 1 0 7s 1 1 1 8s n/a 0 16 5 no function, must be set to 0 tstmp 0 16 8..6 time stamp. the led pulse is generates in the middle of the time stamp range. 8 7 6 values default setting recommended setting 0 0 0 30s x this parameter should be set to the same length as the receive window length, given by the scanning time by the microcontroller. i.e., if the time between the scan commands issued by the micro processor is 60s, this parameter should be set to 60s. 0 0 1 60s 0 1 0 90s 0 1 1 120s 1 0 0 150s 1 0 1 180s 1 1 0 210s 1 1 1 240s drate 0 16 10..9 data rate on the 2-wire bus 10 9 values default setting recommended setting 0 0 250 kbit/s x if the physical 2-wire bus length is up to 100 meters 0 1 500 kbit/s 1 0 1 mbit/s 1 1 2 mbit/s if the physical 2-wire bus length is less than 3 meters ...continued on next page... ? 2011 espros photonics corporation characteristics subject to change without notice 12 datasheet epc12x - v2.1 www.espros.ch
EPC120 parameter name register no. bit no. function ram rom soff 0 16 11 status of voltage regulator for internal vdd 11 values default setting recommended setting 0 on x when used a receiver 1 off when used as interface chip with 3.3v micro controller mode 0 16 14..12 mode for EPC120 usage 14 13 12 value 1 1 0 6 vmode 0 16 15 volatile mode 15 values default setting recommended setting 0 on x this setting allows to overwrite the ram contents, which is useful during debugging. once the system is fully developed, this parameter should be set to 1. this setting could also be useful, if the system parameters should be changed on the fly in dynamic systems. it is recommended to program the address and burn it into the rom first. all other parameters can then be downloaded upon power-up. 1 off set to 1 in the final product to avoid accidentally overwriting of the contents of the ram registers table 3 : EPC120 registers 0 and 16 6. parameter setting registers 1/17 parameter name register no. bit no. function rom ram fusebit 1 17 0 this bit will automatically be set when register 17 is programmed. 0 values 0 register 17 is not programmed 1 register 17 is programmed n/a 1 17 12..1 no function, must be set to 0 tper 1 17 15..13 must be set to 010 15 14 13 0 1 0 table 4 : EPC120 registers 1 and 17 ? 2011 espros photonics corporation characteristics subject to change without notice 13 datasheet epc12x - v2.1 www.espros.ch
EPC120 7. parameter setting registers 2/18 parameter name register no. bit no. function rom ram fusebit 2 18 0 this bit will automatically be set when register 18 is programmed. 0 values 0 register 18 is not programmed 1 register 18 is programmed sensn 2 18 3..1 lower threshold setting of the receiver input (sensitivity). a lower value increases the sens - itivity. a too sensitive setting leads to false readings because of shot noise of the receiver photo diode and the internal amplifier (typ. input noise level is 7na rms without photo di - ode). also induced emi can lead to false readings if the sensitivity is set too low. the emi sensitivity is heavily depending on the system architecture and the electromechanical design. the better the shielding of the chip and the photo diode and the better the pcb layout, the better the emi immunity. the tolerance of the threshold is approx. 25%. 3 2 1 values default setting recommended setting 0 0 0 24na x 0 0 1 36na 0 1 0 48na 0 1 1 60na x 1 0 0 72na 1 0 1 84na 1 1 0 96na 1 1 1 108na sensh 2 18 6..4 upper threshold setting of the receiver input (light reserve level). the tolerance of the threshold is approx. 25%. 6 5 4 values default setting recommended setting 0 0 0 60na x set this value 50% above the value set at sensn, i.e., if sensn is set to 48na, set sensh to 72na 0 0 1 72na 0 1 0 84na 0 1 1 96na 1 0 0 108na 1 0 1 120na 1 1 0 132na 1 1 1 144na slow 2 18 7 no function, must be set to 1 ivcoff 2 18 8 no function, must be set to 0 senslc 2 18 9 must be set to 1 n/a 2 18 12..10 no function, must be set to 0 tset 2 18 15..13 settling time delay from inactive to active mode. 15 14 13 values default setting comments 0 0 0 0 x if t scan >=60s 0 0 1 1 if t scan <60s table 5 : EPC120 registers 2 and 18 ? 2011 espros photonics corporation characteristics subject to change without notice 14 datasheet epc12x - v2.1 www.espros.ch
EPC120 parameter name register no. bit no. function ram rom fusebit 3 19 0 this bit will automatically be set when register 18 is programmed. 0 values 0 register 18 is not programmed 1 register 18 is programmed n/a 3 19 8..1 no function, must be set to 0 c2x 3 19 9 current amplitude on the 2-wire bus 9 values default setting recommended setting 0 8ma x x 1 16ma cdet 3 19 11..10 detection level for the comparator on the 2-wire bus. the level represents the optimum sig - nal amplitude on the bus. 11 10 values default setting recommended setting 0 0 50mv x 0 1 n/a 1 0 100mv 1 1 200mv x tper 3 17 15..13 must be set to 010 15 14 13 0 1 0 table 6 : EPC120 registers 3 and 19 all other registers are factory set and must not be used or altered. 8. sample parameter setting if we are going to use a system with a maximum cable length of 3 meters, and the maximum speed on the 2-wire bus, it is recommended to set the registers as follows: ? 2011 espros photonics corporation characteristics subject to change without notice 15 datasheet epc12x - v2.1 www.espros.ch figure 13 : sample parameter setting for high speed operation bit # rom ram 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e g i s t e r # 0 16 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 x 1 17 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x 2 18 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 x 3 19 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 x 4 20 don't use 5 21 don't use 6 22 don't use 7 23 address don't use 8 24 chip id 9 25 10 26 11 27 12 28 13 29 14 30 15 31
EPC120 9. timing overview to operate the individual elements at the 2-wire bus, some steps per element are necessary. the following drawing shows the concept: the individual EPC120 elements at the 2-wire bus are normally in a sleep mode in order to keep the overall power consumption as low as possible. thus, an EPC120 element has to be activated before it can be used. this wakeup procedure needs a certain time until all internal operating levels have been stabilized. this time is called settling time which can be set with the parameter tset. then, the receive window can be opened and the internal led driver send a pulse out through the led pin, which the chip can receive, if no obstacle is in the light beam. after that, the receive window must be turned off which also puts the receiver to standby. finally, the receive results which are stored in the ecp120 element can be read. in fact, there are several steps to operate one light beam only. this needs quite a long time if everything is done in a strictly sequential way. in order to improve the performance of the whole system, certain steps can be done in parallel. the following chapters describe the timing processes in more detail. timing the microprocessor in the bus controller controls EPC120 with scan commands. every scan command includes an address which selects the requested EPC120 element. pd pin operation: a first scan command switches the selected EPC120 element from standby into operation mode. the process from standby to operation requires a certain time which is called settling time (see figure 15 ). the settling time minimum is 60s. the second scan command opens the the reception window, there also the pulse at the led pin is sent, where a third scan command closes the reception window and puts the EPC120 element back to standby. the fourth scan command fetches the received results. led pin operation: a first scan command switches the selected EPC120 element from standby into operation mode. the process from standby to operation requires a certain time which is called settling time (see figure 15 ). the second scan command starts the light pulse window. after the time pdelay, one light pulse of the length tpulse is generated. a third scan command puts the element back to standby. if the tstmp and the period of the scan commands of the microprocessor are equal the pulse will be emitted exactly in the middle of the reception window. the whole operation is optimized for shortest possible scan periods. figure 15 shows the timing for a settling time of one scan period (tset=0) and the add resses given in the shortest possible sequence. ? 2011 espros photonics corporation characteristics subject to change without notice 16 datasheet epc12x - v2.1 www.espros.ch wakeup the EPC120 element (from standby to operation) open the receive window and send a light pulse out through the led pin after pdelay close the receive window and put the device to standby rx & tx read the result of the last light reception figure 14 : basic sequence to operate one light beam. note that the process in the receiver and in the transmitter are running concurrently.
EPC120 figure 15 : timing of the scan process where n = element number t scan = interval between two scan commands which is given by the micro processor the minimum delay time between the first scan command and the earliest possible access of the result can be calculated as a function of the parameter tset and the scan period t scan : t del = tset 3 ? t scan the sensor device counts the number of scan commands on the bus to present its result at the right time. if the number of a scan command is n, the result will arrive with the scan command n+tset+3 . the timing of the emitter commands have to be adjusted in order to emit the light pulse near the center of the reception window of the corres - ponding receiver. e.g. if the reception window length is set to 30 s, the light pulse shall be generated 15s after the opening of the receive window. the length of the reception window is defined by the time elapsed between the second and the third scan command. the parameter tstmp defines the time window to measure the arrival time of the received light pulse. this result is returned in the result timestamp. the timing position of the following light pulses can be optimized to the center of the receiving window. the resolution of timestamp is 4 bits. thus, the value is 0000 if the pulse is received at the beginning of the window, and 1111 if it arrived at the end. a light pulse received approx. in the middle of the receive window would be represented as 0011, 0100 or 0101. the minimal scan period, which is the time between two consecutive scan commands, is given by the communication on the 2-wire bus: 62 bits for the command and the results have to be transmitted in this time. the minimal scan period is then t scanmin = 31 ? t clk ? k k is given by the parameter drate and varies between 1 and 8 (refer to table 1 , table 3 and table 7 ). t clk is 1s. thus, the minimal scan period is 31s. special cases ? if the same device is addressed again at the end of its reception window, it continues waiting for pulses. this procedure allows to synchronize the receiver with the transmitter on an optical basis, if there is no electrical synchronization. ? if a device detects a command during a scan operation which is not the command scan, it is put into standby mode. ? a scan command with address 0 can be used to fetch the results without starting a new scan command. ? 2011 espros photonics corporation characteristics subject to change without notice 17 datasheet epc12x - v2.1 www.espros.ch <name> 14.09.2010 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . spi in spi out 2-wire bus pd n pd n+1 pd n+2 scan n scan n scan n+1 scan n+2 scan n+3 scan n+4 scan n+5 scan n+1 scan n+2 scan n+3 scan n+4 out n out n+1 out n+2 out n out n+1 out n+2 t del settling receive window output, standby settling receive window output, standby settling receive window output, standby t scan led n led n+1 led n+2 settling standby settling standby settling standby t pdelay t pulse t set <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> 10. spi interface the spi interface allows the microcontroller to communicate with the sensors over the 2-wire bus system via the interface device. while data are sent to the interface chip by the microcontroller, the result of the last (or more generally: a previous) command is sent from the interface chip to the microcontroller according to the spi protocol. the timing diagram is shown in figure 16 ). figure 16 : spi bus timing timing specification spi interface symbol parameter conditions/comments values units min. typ. max. f sck sck clock frequency 10 mhz t h / t l high and low period of sck 50 ns t su / t hold set-up and hold time si 15 ns t 1 edge time csb - sck 50 ns t rf / t rfsck rise / fall time so, sck 20 ns t d data valid after sck edge so 20 ns command overview general description communication is based on telegrams, which are sent and received over the 2-wire bus. such telegrams are initiated by the respective command to the spi interface. the epc10x chips accept two types of commands: 1. commands which communicate to the interface chips, also called direct commands ( figure 17 ). 2. commands which communicate to the chips at the 2-wire bus, also called broadcast commands ( figure 18 ). the first bit in the data stream from the microprocessor to the interface chip (si pin) defines whether it is a command to the interface chip (a 0) or the the chips on the 2-wire bus (a 1). figure 17 : communication to the interface device (direct command) ? 2011 espros photonics corporation characteristics subject to change without notice 18 datasheet epc12x - v2.1 www.espros.ch timing spi interface epc100 lst cs sck si so t l t h 03.11.2010 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . t hold 1/f sck t 1 t su t d 26.05.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . cs sck si c 0 c 1 c 2 r 0 r 1 r 2 r 3 r 4 d 0 d 1 d n command register address or cmd extension data <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> figure 18 : communication to the sensor devices (broadcast command) command list name command code c 0 .. c 2 command extension code r 0 .. r 4 function mode number of data bits on 2-wire bus d 0 ..d n returned data scan 000 scan broadcast 62 yes nop 000 no operation direct 0 yes read 010 register address read both 97 yes write 011 register address write to volatile register both 62 no adra 101 address allocation broadcast 62 no prog 110 register address program both 62 no test 111 10000 test mode both 80 yes reset 111 11001 reset the device both 62 no table 7 : command list remarks : ? additional sck clock cycles have no effect. ? th e telegram length on the 2-wire bus is given in the number of data clock cycles. it allows to calculate the minimum int erval between two commands. ? if an spi command is given while another command is being transmitted on the 2-wire bus, the new command is ig nored. ? the read and write commands in the direct access mode require 2 additional sck cycles. command scan the command scan enables the addressed device, times the ongoing operation or fetches the scan result. the operation of the command scan is described more in detail in c hapter error: reference source not found . the bit n indicates whether a new result has been received. d 0 ...d 4 contains the address, d 11 ...d 20 contains the returned data, e 0 ...e 3 contains an error code. d 5 ...d 10 are empty. ? 2011 espros photonics corporation characteristics subject to change without notice 19 datasheet epc12x - v2.1 www.espros.ch <text> m 1:1 <date> din a3 <partname> <x000 000> <text> designed approved scale page t h i s d o c u m e n t i s c o n f i d e n t i a l a n d p r o t e c t e d b y l a w a n d i n t e r n a t i o n a l t r a d e s . i t m u s t n o t b e s h o w n t o a n y t h i r d p a r t y n o r b e c o p i e d i n a n y f o r m w i t h o u t o u r w r i t t e n p e r m i s s i o n . file: part name part no. 1 26.02.2009 cs sck si a0 a1 a2 a3 a4 r0 a8 a9 d0 d1 dn r1 r2 r3 r4 c0 c1 c2 device address command register address or cmd extension data figure 19 : timing of the results of a scan command 26.05.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . cs sck si n d 0 d 1 d 2 d 3 d 4 d 5 d 20 e 0 e 3 <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> data bits function n indicates, if new data is available n values 0 no new data available 1 new data available d 0 d 3 timestamp d 4 status of receiver threshold normal d 4 values 0 receiver threshold set by sensn not reached 1 receiver threshold set by sensn exceeded d 5 status of receiver threshold high (light reserve) d 4 values 0 receiver threshold set by sensh not reached 1 receiver threshold set by sensh exceeded d 5 d 10 empty, not used d 11 d 20 device address e 0 e 3 error codes, refer to chapter error codes table 8 : result of a scan command command nop the command nop can be used to fetch the last received data without sending a new command. with this command it is possible to monitor the 2-wire interface by a second interface device in a redundant system. command test the command test issues an internal test pulse or a dc current at the pd input pin on a specific receiver. it simulates basically a received light pulse or dc sunlight influence to check the proper functionality of the receiver(s) without using an emitter. this mode is initialized by the command test and is left after a complete scan sequence. code c 0 c 2 extension r 0 r 4 amplitude d 0 d 4 current shape 111 10000 1xxxxx x1xxxx xx1xxx xxx1xx xxxx1x xxxxx1 25na 50na 100na 100 a 500 a dc 2ma dc pulse pulse pulse pulse dc dc table 9 : self test the applied current is the sum of different current sources: in column pulse amplitude of table 9 a 1 means, that the corresponding current is added. example: 110000 generates a pulse of 75na without dc. command reset the command reset resets the device and initiates a startup. all devices can be reset simultaneously by using address 0. command adra adra is used during the configuration of a light curtain system to allocate a logical address to the physical position of the the emitter or receiver element. the command adra stores the device address to the volatile memory only (ram). if the device address has to be stored permanently, the command prog has to be used to copy the previous stored device address from the ram register into the rom register. adra can only be used if there was no previous prog command to the address register. the address 0 is reserved to address all devices together or none and must not be used as an individual address. the command adra generates no result. for details refer to chapter address programming . ? 2011 espros photonics corporation characteristics subject to change without notice 20 datasheet epc12x - v2.1 www.espros.ch <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> command read the ram and rom can be read by the command read. the command is extended by the register address. figure 20 : timing result data the bit n indicates whether a new result has been received (broadcast mode). d 0 ...d 4 contains the address, d 11 ...d 20 contains the returned data. data bits function n indicates, if new data is available n values 0 no new data available 1 new data available d 0 d 4 5 bit register address d 5 d 20 16 bit returned data (one complete register) table 10 : result of a read command command write data can be written into the ram by using the command write. the command is extended by the register address and the data. it is only possible to write to registers if the corresponding register in the rom has not been written yet. it is not possible to write directly to a rom register. if the data has to be stored into the rom register, a subsequent command prog has to be used. command prog the command prog transfers the data from the ram register to the corresponding rom register. see chapter address programming for a detailed description. returned results the results at pin so depends on one of the previous commands and can be fetched by any command or just by toggling sck while cs is low (=nop). ? the data is represented with the lsb first. ? after an spi communication the data register is cleared. ? by holding the cs line to 0 it is possible to trigger on a positive edge of so. ? if more clock toggles sck are issued than data can be fetched, zeros are transmitted. ? 2011 espros photonics corporation characteristics subject to change without notice 21 datasheet epc12x - v2.1 www.espros.ch <timming spi read command 1> <lst> 10.09.2010 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . cs sck si n d 0 d 1 d 2 d 3 d 4 d 5 d 20 <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> 11. address programming general description the device address is initially set to 00000 and the devices are not parametrized. however, all devices hold a unique chip id. however, due to the 2-wire bus concept, the physical location of an individual device is not known to the microcontroller . in order to operate the light curtain, the microcontroller needs to allocate a specific receiver to a specific emitter. usually, the receiver at one end of the 2-wire bus gets the address 1, the next receiver the address 2 and so on. the same must be done on the emitter side. once all devices on the receiver and on the emitter side got their address, the microcontroller can operate the light curtain. the address allocation, meaning the allocation of a physical location to a logical address, is usually done in the factory of the light curtain manufacturer. to do so, a specific address allocation procedure together with the parametrization of the devices must be executed first. the following procedure is an example how to allocate a unique address and how to parametrize each device. no. step description 1 set the address of the interface device set the address of the interface device with a direct command to a fix number, which should not be 0. it is recommended to use generally the address 1023 for the interface device. 2 parametrize the devices on the 2- wire bus the data rate drate of the 2-wire interface is initially set to 300 kbit/s. it shall be set to the correct value by addressing all devices, which are initially at address 0, simultaneously. during this step, all other parameters in register 16 can also be set. 3 parametrize the interface device the data rate of the 2-wire interface is initially set to 300 kbit/s. it has to be set to the same value like the other devices on the same 2-wire bus. 4 set all other registers for the address allocation the following parameters should be set: tper = 2 sensn = 7 slow=1 this can be done to all devices at the same time by writing the registers to device 0. 5 address allo cation since the devices have an open receive window, all of them are able to receive light pulses. this mode is used to allocate the logical address to the physical location. the procedure is as follows: ? issue the command adra using address n ? flash a light pulse to the photo diode which is connected to the chip at the physical position n (make sure that all the other photo diodes cannot receive a light pulse). by receiving a light pulse, the address n is stored into the ram of the element at the physical position n. thus, the device, which receives a light pulse, memorizes the address n as its own address in the final system. this procedure has to be repeated for every individual element on the 2-wire bus. it is recommended to start with the address 1 for the element which is closest to the controller and increment the address by 1 with every individual element. in the case of a 20-beam light curtain, addresses from 1 to 20 on the receiv - er and on the emitter side are accessible. however, the interface chip is usually located at address 1023. 6 address check it is recommended to check the correct address setting by addressing every device in the system using the read command. all devices addressed shall response to the read command. 7 address programming once all addresses of all devices at the 2-wire bus are stored into the ram (register 23), the address should be transferred to the rom (register 7) for each device separately by using the command prog. please refer to chapter 11. address programming . 8 set parameters parameters like tstmp, mode, vmode, tpulse etc. are stored into the ram of all devices using the command write. if the global address 0 is used, all devices receive the parameters at the same time. since the internal voltage regulator of the interface device is not needed, the parameter soff has to be set to 1 (refer to table 3 ). all other devices at the 2-wire bus must have a 0 for soff. 9 check parameters the parameters should be checked by reading them back from each device using the read command. 10 program parameters if all parameters are stored correctly, store the parameters into the non-volatile memory by using the command prog. 11 test programming and addressing to check the programming of addresses and parameters, turn off the power supply or reset all devices and readout all addresses and parameters again. ? 2011 espros photonics corporation characteristics subject to change without notice 22 datasheet epc12x - v2.1 www.espros.ch <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> programming procedure programming the device is a transfer of the data from the ram to the corresponding rom register. each 16-bit register must be transferred individually. thus, register 16 is transferred to register 0, register 17 to register 1, register 18 to register 2, register 19 to register 3, and register 23 to register 7. all other registers must not be used. figure 21 shows the timing of the programming sequence for one register: figure 21 : direct programming procedure prog is the prog command sequence (110). register means the address of the target register (rom), e.g. 0, 1, 2, 3, 7. during programming, the voltage at pin vdd has to be increased to v prog ( 7.5v) and has to be kept stable buffered during the whole programming cycle. the timing parameters given in figure 21 and figure 22 have to be obeyed. remarks: ? it is possible to program more than one register during a vdd high cycle. between two prog commands a delay of 400 s is needed. ? each register can be programmed once only (otp). ? after programming a register, bit no. 0 of this register becomes automatically a one to indicate that the register is programmed. ? 2011 espros photonics corporation characteristics subject to change without notice 23 datasheet epc12x - v2.1 www.espros.ch figure 22 : broadcast programming procedure r0 r1 r2 r3 r4 sck cs vdd si 400s 50s prog register 1 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 device address 5v 7.5v r0 r1 r2 r3 r4 sck cs vdd si 400s 50s 5v 7.5v prog register 1 1 0 <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> 12. considerations for safety applications since the <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a>-family chips can be used in safety related products, like machine safety light products, certain data integrity mechanisms have been integrated. the safety concept on chip and communication level are described in this chapter. data integrity on the 2-wire power-bus several mechanisms on different layers are implemented to guarantee a low residual error rate on the 2-wire power-bus. physical layer ? modulation and medium: current modulation on a twisted pair line is highly immune to interference. ? start bit detection: the start pulse must have the correct orientation. otherwise, the pulse is discarded. ? pulse alternation: since manchester coding is used, the pulses need to alternate. an error is detected, if this is not the case. ? pulse timing: the timing of the information pulses is fixed. a missing bit (too long pause) is detected as an error. ? end bit detection: since current modulation is used and the current is switched off when the message is completed, the last pulse has a specified orientation. ? sequence length: the message length is well known. a too short or too long message is detected as an error. data link layer ? error control coding: if no errors have been detected on the physical layer, the received pulse sequence is processed by an error control algorithm. depending on the application, either 2 errors can be corrected, or 4 errors can be detected. a higher number of errors can be detected with a reliability of 1000:1. ? strict master-slave system: a sensor may only respond, if a request from the microcontroller was correctly received. ? explicit addressing: each message (master > slave and slave > master) contains the address of the sensor element. even if the wrong sensor replies to the microcontroller call, the error will be detected. residual error rate although no explicit calculations have been done yet, the residual error rate of the 2-wire power-bus is at least as good as in the asi. the asi has an residual error probability of a system with hamming distance 5 (hd5) and belongs to the din 19244 data integrity class i2 for an error probability p=1e-2, and to class i3 for p=1e-3. error cases each sensor device has its unique address. the microprocessor addresses each device individually and fetches the result some scan periods later. the result includes also the address of the answering device. error cases consequences 2 sensor answer on the same address collision during the transmission of the result. error detection in the interface device error state. error during the scan command no device answers no data (all zero). error during result transmission error detection in the interface device error state. error codes different error states are monitored: device error action error code e0 e3 1 sensor non-correctable error in the received telegram device doesn't response - 2 sensor command to fetch the result too early normal answer - 4 interface no answer from the sensor device result data zero - 5 interface non-correctable error in the received telegram error reported 1xxx *) 6 interface return telegram not complete error handling procedure 0100 table 11 : error states *) the last three error bits contain the number of detected errors. ? 2011 espros photonics corporation characteristics subject to change without notice 24 datasheet epc12x - v2.1 www.espros.ch <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> layout information (all measures in mm, <partname> <x000 000> <name> <data> m 1:1 din a4 <name> part name part no. designed approved scale page t h i s d o c u m e n t i s c o n f i d e n t i a l a n d p r o t e c t e d b y l a w a n d i n t e r n a t i o n a l t r a d e s . i t m u s t n o t b e s h o w n t o a n y t h i r d p a r t y n o r b e c o p i e d i n a n y f o r m w i t h o u t o u r w r i t t e n p e r m i s s i o n . file: unbenannt 1 26.02.2009 ) csp-10 package 0 . 5 1.9 +0.0/-0.1 1 . 4 + 0 . 0 / - 0 . 1 0.5 0.5 0.15 0 . 1 5 0 . 5 solder balls sn97.5ag2.5 0 . 3 0 . 1 1 0 . 0 1 ? 0.12 bottom view pin 1 figure 23 : csp10: mechanical dimensions <title> <name> 19.01.2012 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . no solder mask inside this area 0.5 0.5 0 . 5 ? 0.3 2.5 2 . 0 0.1524 figure 24 : csp10: layout recommendation qfn-16 package mechanical dimension qfn16 package lst mechanical dimension sot23-6l lst top view 2 . 9 - 3 . 1 2.9 - 3.1 1.9 0.25 15.08.2010 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 0.5 0 . 9 bottom view 0 . 2 5 1 . 9 0.3 0 . 1 - 0 . 2 0 . 0 2 figure 25 : qfn-16: mechanical dimensions ? 2011 espros photonics corporation characteristics subject to change without notice 25 datasheet epc12x - v2.1 www.espros.ch <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> reflow solder profile for infrared or conventional soldering the solder profile has to follow the recommendations of ipc/jedec j-std-020c (min. revision c) for pb-free assembly for both types of packages. the peak soldering t emperature (t l ) should not exceed +260c for a maximum of 4 sec. packaging information (all measures in mm) tape & reel information the devices are mounted on embossed tape for automatic placement systems. the tape is wound on 178 mm (7 inch) or 330 mm (13 inch) reels and individually packaged for shipment. g eneral tape-and-reel specification data are available in a separate data sheet and indicate the tape sizes for various package types. further tape-and-reel specifications can be found in the electronic industries association (eia) standard 481-1, 481-2, 481-3. pin 1 8 pin 1 1 2 8 2 csp6 tape qfn16 tape pin 1 8 pin 1 1 2 8 4 csp6 tape qfn16 tape figure 26 : csp10 and qfn16 tape dimensions espros photonics ag does not guarantee that there are no empty cavities. thus, the pick-and-place machine should check the presence of a chip during picking. ordering information type package rohs compliance packaging method <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a>-csp10 csp10 yes reel <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a>-qfn16 qfn16 yes reel ? 2011 espros photonics corporation characteristics subject to change without notice 26 datasheet epc12x - v2.1 www.espros.ch <br> <a href='http://www.datasheet.hk/search.php?part=epc120&stype=part'>EPC120</a> important notice espros photonics ag and its subsidiaries (epc) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to epcs terms and conditions of sale supplied at the time of order acknowledgment. epc warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with epcs standard war - ranty. testing and other quality control techniques are used to the extent epc deems necessary to support this warranty. except where man - dated by government requirements, testing of all parameters of each product is not necessarily performed. epc assumes no liability for applications assistance or customer product design. customers are responsible for their products and applic - ations using epc components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. epc does not warrant or represent that any license, either express or implied, is granted under any epc patent right, copyright, mask work right, or other epc intellectual property right relating to any combination, machine, or process in which epc products or services are used. information published by epc regarding third-party products or services does not constitute a license from epc to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from epc under the patents or other intellectual property of epc. resale of epc products or services with statements different from or beyond the parameters stated by epc for that product or service voids all express and any implied warranties for the associated epc product or service. epc is not responsible or liable for any such statements. epc products are not authorized for use in safety-critical applications (such as life support) where a failure of the epc product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of epc products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by epc. further, buyers must fully indemnify epc and its representatives against any damages arising out of the use of epc products in such safety-critical applications. epc products are neither designed nor intended for use in military/aerospace applications or environments unless the epc products are spe - cifically designated by epc as military-grade or "enhanced plastic." only products designated by epc as military-grade meet military specific - ations. buyers acknowledge and agree that any such use of epc products which epc has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. epc products are neither designed nor intended for use in automotive applications or environments unless the specific epc products are desig nated by epc as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, epc will not be responsible for any failure to meet such requirements. ? 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